Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 7) (2018)
=====================================================================================================

This is the seventh edition of the `CHERI
<https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/>`_ instruction set
architecture definition.  Much of my contribution is to the experimental
appendix.

The document is available at the official repository as
`UCAM-CL-TR-927 <https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-927.html>`_
or by local mirror :download:`here <2018-cheri-isav7.pdf>`.


BibTeX:

.. code-block:: none
    
    @TechReport{watson:cheriisav7,
      author  = {Watson, Robert N. M. and Neumann, Peter G. and Woodruff,
                Jonathan and Roe, Michael and Almatary, Hesham and Anderson,
                Jonathan and Baldwin, John and Chisnall, David and Davis, Brooks
                and Filardo, Nathaniel Wesley and Joannou, Alexandre and Laurie,
                Ben and Moore, Simon W. and Murdoch, Steven J. and Nienhuis,
                Kyndylan and Norton, Robert and Richardson, Alex and Rugg, Peter
                and Sewell, Peter and Son, Stacey and Xia, Hongyan},
      title   = {{Capability Hardware Enhanced RISC Instructions: CHERI
                Instruction-Set Architecture (Version 7)}},
      year    = {2018},
      month   = 10,
      url     = {https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-927.pdf},
      institution={University of Cambridge, Computer Laboratory},
      number  = {UCAM-CL-TR-927}
    }