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Publications by author
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Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 7) (PDF) (Cached: PDF) by Robert N. M. Watson, Peter G. Neumann, Jonathan Woodruff, Michael Roe, Hesham Almatary, Jonathan Anderson, John Baldwin, David Chisnall, Brooks Davis, Nathaniel Wesley Filardo, Alexandre Joannou, Ben Laurie, Simon W. Moore, Steven J. Murdoch, Kyndylan Nienhuis, Robert Norton, Alex Richardson, Peter Rugg, Peter Sewell, Stacey Son, and Hongyan Xia.
University of Cambridge, Computer Laboratory technical report UCAM-CL-TR-927, October 2018. (BibTeX entry)·
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Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 7) (PDF) (Cached: PDF) by Robert N. M. Watson, Peter G. Neumann, Jonathan Woodruff, Michael Roe, Hesham Almatary, Jonathan Anderson, John Baldwin, David Chisnall, Brooks Davis, Nathaniel Wesley Filardo, Alexandre Joannou, Ben Laurie, Simon W. Moore, Steven J. Murdoch, Kyndylan Nienhuis, Robert Norton, Alex Richardson, Peter Rugg, Peter Sewell, Stacey Son, and Hongyan Xia.
University of Cambridge, Computer Laboratory technical report UCAM-CL-TR-927, October 2018. (BibTeX entry)·
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Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 7) (PDF) (Cached: PDF) by Robert N. M. Watson, Peter G. Neumann, Jonathan Woodruff, Michael Roe, Hesham Almatary, Jonathan Anderson, John Baldwin, David Chisnall, Brooks Davis, Nathaniel Wesley Filardo, Alexandre Joannou, Ben Laurie, Simon W. Moore, Steven J. Murdoch, Kyndylan Nienhuis, Robert Norton, Alex Richardson, Peter Rugg, Peter Sewell, Stacey Son, and Hongyan Xia.
University of Cambridge, Computer Laboratory technical report UCAM-CL-TR-927, October 2018. (BibTeX entry)·
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Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 7) (PDF) (Cached: PDF) by Robert N. M. Watson, Peter G. Neumann, Jonathan Woodruff, Michael Roe, Hesham Almatary, Jonathan Anderson, John Baldwin, David Chisnall, Brooks Davis, Nathaniel Wesley Filardo, Alexandre Joannou, Ben Laurie, Simon W. Moore, Steven J. Murdoch, Kyndylan Nienhuis, Robert Norton, Alex Richardson, Peter Rugg, Peter Sewell, Stacey Son, and Hongyan Xia.
University of Cambridge, Computer Laboratory technical report UCAM-CL-TR-927, October 2018. (BibTeX entry)·
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Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 7) (PDF) (Cached: PDF) by Robert N. M. Watson, Peter G. Neumann, Jonathan Woodruff, Michael Roe, Hesham Almatary, Jonathan Anderson, John Baldwin, David Chisnall, Brooks Davis, Nathaniel Wesley Filardo, Alexandre Joannou, Ben Laurie, Simon W. Moore, Steven J. Murdoch, Kyndylan Nienhuis, Robert Norton, Alex Richardson, Peter Rugg, Peter Sewell, Stacey Son, and Hongyan Xia.
University of Cambridge, Computer Laboratory technical report UCAM-CL-TR-927, October 2018. (BibTeX entry)·
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Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 7) (PDF) (Cached: PDF) by Robert N. M. Watson, Peter G. Neumann, Jonathan Woodruff, Michael Roe, Hesham Almatary, Jonathan Anderson, John Baldwin, David Chisnall, Brooks Davis, Nathaniel Wesley Filardo, Alexandre Joannou, Ben Laurie, Simon W. Moore, Steven J. Murdoch, Kyndylan Nienhuis, Robert Norton, Alex Richardson, Peter Rugg, Peter Sewell, Stacey Son, and Hongyan Xia.
University of Cambridge, Computer Laboratory technical report UCAM-CL-TR-927, October 2018. (BibTeX entry)·
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Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 7) (PDF) (Cached: PDF) by Robert N. M. Watson, Peter G. Neumann, Jonathan Woodruff, Michael Roe, Hesham Almatary, Jonathan Anderson, John Baldwin, David Chisnall, Brooks Davis, Nathaniel Wesley Filardo, Alexandre Joannou, Ben Laurie, Simon W. Moore, Steven J. Murdoch, Kyndylan Nienhuis, Robert Norton, Alex Richardson, Peter Rugg, Peter Sewell, Stacey Son, and Hongyan Xia.
University of Cambridge, Computer Laboratory technical report UCAM-CL-TR-927, October 2018. (BibTeX entry)·
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Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 7) (PDF) (Cached: PDF) by Robert N. M. Watson, Peter G. Neumann, Jonathan Woodruff, Michael Roe, Hesham Almatary, Jonathan Anderson, John Baldwin, David Chisnall, Brooks Davis, Nathaniel Wesley Filardo, Alexandre Joannou, Ben Laurie, Simon W. Moore, Steven J. Murdoch, Kyndylan Nienhuis, Robert Norton, Alex Richardson, Peter Rugg, Peter Sewell, Stacey Son, and Hongyan Xia.
University of Cambridge, Computer Laboratory technical report UCAM-CL-TR-927, October 2018. (BibTeX entry)·
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Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 7) (PDF) (Cached: PDF) by Robert N. M. Watson, Peter G. Neumann, Jonathan Woodruff, Michael Roe, Hesham Almatary, Jonathan Anderson, John Baldwin, David Chisnall, Brooks Davis, Nathaniel Wesley Filardo, Alexandre Joannou, Ben Laurie, Simon W. Moore, Steven J. Murdoch, Kyndylan Nienhuis, Robert Norton, Alex Richardson, Peter Rugg, Peter Sewell, Stacey Son, and Hongyan Xia.
University of Cambridge, Computer Laboratory technical report UCAM-CL-TR-927, October 2018. (BibTeX entry)·
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Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 7) (PDF) (Cached: PDF) by Robert N. M. Watson, Peter G. Neumann, Jonathan Woodruff, Michael Roe, Hesham Almatary, Jonathan Anderson, John Baldwin, David Chisnall, Brooks Davis, Nathaniel Wesley Filardo, Alexandre Joannou, Ben Laurie, Simon W. Moore, Steven J. Murdoch, Kyndylan Nienhuis, Robert Norton, Alex Richardson, Peter Rugg, Peter Sewell, Stacey Son, and Hongyan Xia.
University of Cambridge, Computer Laboratory technical report UCAM-CL-TR-927, October 2018. (BibTeX entry)·
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The Foundations of a Provably Secure Operating System (PSOS) (PDF) (Cached: PDF) by R. J. Feiertag and P. G. Neumann.
In the Proceedings of the National Computer Conference, 1979, pages 329-334. (BibTeX entry)·
Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 7) (PDF) (Cached: PDF) by Robert N. M. Watson, Peter G. Neumann, Jonathan Woodruff, Michael Roe, Hesham Almatary, Jonathan Anderson, John Baldwin, David Chisnall, Brooks Davis, Nathaniel Wesley Filardo, Alexandre Joannou, Ben Laurie, Simon W. Moore, Steven J. Murdoch, Kyndylan Nienhuis, Robert Norton, Alex Richardson, Peter Rugg, Peter Sewell, Stacey Son, and Hongyan Xia.
University of Cambridge, Computer Laboratory technical report UCAM-CL-TR-927, October 2018. (BibTeX entry)·
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Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 7) (PDF) (Cached: PDF) by Robert N. M. Watson, Peter G. Neumann, Jonathan Woodruff, Michael Roe, Hesham Almatary, Jonathan Anderson, John Baldwin, David Chisnall, Brooks Davis, Nathaniel Wesley Filardo, Alexandre Joannou, Ben Laurie, Simon W. Moore, Steven J. Murdoch, Kyndylan Nienhuis, Robert Norton, Alex Richardson, Peter Rugg, Peter Sewell, Stacey Son, and Hongyan Xia.
University of Cambridge, Computer Laboratory technical report UCAM-CL-TR-927, October 2018. (BibTeX entry)·
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Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 7) (PDF) (Cached: PDF) by Robert N. M. Watson, Peter G. Neumann, Jonathan Woodruff, Michael Roe, Hesham Almatary, Jonathan Anderson, John Baldwin, David Chisnall, Brooks Davis, Nathaniel Wesley Filardo, Alexandre Joannou, Ben Laurie, Simon W. Moore, Steven J. Murdoch, Kyndylan Nienhuis, Robert Norton, Alex Richardson, Peter Rugg, Peter Sewell, Stacey Son, and Hongyan Xia.
University of Cambridge, Computer Laboratory technical report UCAM-CL-TR-927, October 2018. (BibTeX entry)·
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Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 7) (PDF) (Cached: PDF) by Robert N. M. Watson, Peter G. Neumann, Jonathan Woodruff, Michael Roe, Hesham Almatary, Jonathan Anderson, John Baldwin, David Chisnall, Brooks Davis, Nathaniel Wesley Filardo, Alexandre Joannou, Ben Laurie, Simon W. Moore, Steven J. Murdoch, Kyndylan Nienhuis, Robert Norton, Alex Richardson, Peter Rugg, Peter Sewell, Stacey Son, and Hongyan Xia.
University of Cambridge, Computer Laboratory technical report UCAM-CL-TR-927, October 2018. (BibTeX entry)·
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Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 7) (PDF) (Cached: PDF) by Robert N. M. Watson, Peter G. Neumann, Jonathan Woodruff, Michael Roe, Hesham Almatary, Jonathan Anderson, John Baldwin, David Chisnall, Brooks Davis, Nathaniel Wesley Filardo, Alexandre Joannou, Ben Laurie, Simon W. Moore, Steven J. Murdoch, Kyndylan Nienhuis, Robert Norton, Alex Richardson, Peter Rugg, Peter Sewell, Stacey Son, and Hongyan Xia.
University of Cambridge, Computer Laboratory technical report UCAM-CL-TR-927, October 2018. (BibTeX entry)·
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Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 7) (PDF) (Cached: PDF) by Robert N. M. Watson, Peter G. Neumann, Jonathan Woodruff, Michael Roe, Hesham Almatary, Jonathan Anderson, John Baldwin, David Chisnall, Brooks Davis, Nathaniel Wesley Filardo, Alexandre Joannou, Ben Laurie, Simon W. Moore, Steven J. Murdoch, Kyndylan Nienhuis, Robert Norton, Alex Richardson, Peter Rugg, Peter Sewell, Stacey Son, and Hongyan Xia.
University of Cambridge, Computer Laboratory technical report UCAM-CL-TR-927, October 2018. (BibTeX entry)·
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Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 7) (PDF) (Cached: PDF) by Robert N. M. Watson, Peter G. Neumann, Jonathan Woodruff, Michael Roe, Hesham Almatary, Jonathan Anderson, John Baldwin, David Chisnall, Brooks Davis, Nathaniel Wesley Filardo, Alexandre Joannou, Ben Laurie, Simon W. Moore, Steven J. Murdoch, Kyndylan Nienhuis, Robert Norton, Alex Richardson, Peter Rugg, Peter Sewell, Stacey Son, and Hongyan Xia.
University of Cambridge, Computer Laboratory technical report UCAM-CL-TR-927, October 2018. (BibTeX entry)·
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Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 7) (PDF) (Cached: PDF) by Robert N. M. Watson, Peter G. Neumann, Jonathan Woodruff, Michael Roe, Hesham Almatary, Jonathan Anderson, John Baldwin, David Chisnall, Brooks Davis, Nathaniel Wesley Filardo, Alexandre Joannou, Ben Laurie, Simon W. Moore, Steven J. Murdoch, Kyndylan Nienhuis, Robert Norton, Alex Richardson, Peter Rugg, Peter Sewell, Stacey Son, and Hongyan Xia.
University of Cambridge, Computer Laboratory technical report UCAM-CL-TR-927, October 2018. (BibTeX entry)·
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Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 7) (PDF) (Cached: PDF) by Robert N. M. Watson, Peter G. Neumann, Jonathan Woodruff, Michael Roe, Hesham Almatary, Jonathan Anderson, John Baldwin, David Chisnall, Brooks Davis, Nathaniel Wesley Filardo, Alexandre Joannou, Ben Laurie, Simon W. Moore, Steven J. Murdoch, Kyndylan Nienhuis, Robert Norton, Alex Richardson, Peter Rugg, Peter Sewell, Stacey Son, and Hongyan Xia.
University of Cambridge, Computer Laboratory technical report UCAM-CL-TR-927, October 2018. (BibTeX entry)·
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Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 7) (PDF) (Cached: PDF) by Robert N. M. Watson, Peter G. Neumann, Jonathan Woodruff, Michael Roe, Hesham Almatary, Jonathan Anderson, John Baldwin, David Chisnall, Brooks Davis, Nathaniel Wesley Filardo, Alexandre Joannou, Ben Laurie, Simon W. Moore, Steven J. Murdoch, Kyndylan Nienhuis, Robert Norton, Alex Richardson, Peter Rugg, Peter Sewell, Stacey Son, and Hongyan Xia.
University of Cambridge, Computer Laboratory technical report UCAM-CL-TR-927, October 2018. (BibTeX entry)·
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Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 7) (PDF) (Cached: PDF) by Robert N. M. Watson, Peter G. Neumann, Jonathan Woodruff, Michael Roe, Hesham Almatary, Jonathan Anderson, John Baldwin, David Chisnall, Brooks Davis, Nathaniel Wesley Filardo, Alexandre Joannou, Ben Laurie, Simon W. Moore, Steven J. Murdoch, Kyndylan Nienhuis, Robert Norton, Alex Richardson, Peter Rugg, Peter Sewell, Stacey Son, and Hongyan Xia.
University of Cambridge, Computer Laboratory technical report UCAM-CL-TR-927, October 2018. (BibTeX entry)·
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